A simplified gate-level fault model for crosstalk effects analysis

被引：1
|
作者：
Civera, P [1 ]
Macchiarulo, L [1 ]
Violante, M [1 ]
机构：
[1] Politecn Torino, Dipartimento Elettron, I-10129 Turin, Italy
来源：
17TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS | 2002年
关键词：
D O I：
10.1109/DFTVS.2002.1173499
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The relevant problem of crosstalk affects the design process in many ways. Its delay effects can not be easily addressed due to the complex interaction between signals and dependency on the logical, functional and timing aspects of the design. In this paper we propose a modelling approach and a methodology to assess crosstalk effects on real designs through a simulation-based analysis environment. Results are reported showing how the proposed approach has been used to validate the bus architecture inside the LEON SPARC-like processor core.
引用
收藏
页码：31 / 39
页数：9
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