Reconfigurable implementation of GF(2m) bit-parallel multipliers

Hardware implementations of arithmetic operations over binary finite fields GF(2(m)) are widely used in several important applications, such as cryptography, digital signal processing and error-control codes. In this paper, efficient. reconfigurable implementations of bit-parallel canonical basis multipliers over binary fields generated by type II irreducible pentanomials f(y) = y(m) + y(n+2) + y(n+1) + y(n) + 1 are presented. These pentanomials are important because all five binary fields recommended by NIST for ECDSA can be constructed using such polynomials. In this work, a new approach for CF(2(m)) multiplication based on type II pentanomials is given and several post-place and route implementation results in Xilinx Artix-7 FPGA are reported. Experimental results show that the proposed multiplier implementations improve the area x time parameter when compared with similar multipliers found in the literature.