共 50 条
- [2] VLSI architecture design of modified Euclidean algorithm for reed-solomon code [J]. 2003 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS, 2003, : 304 - 306
- [3] VLSI Architecture for Reed-Solomon Decoder [J]. JOURNAL OF SPACECRAFT TECHNOLOGY, 2011, 21 (02): : 1 - 11
- [7] A Low Complexity VLSI Architecture for Reed-Solomon Decoder [J]. ICSPC: 2007 IEEE INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND COMMUNICATIONS, VOLS 1-3, PROCEEDINGS, 2007, : 1551 - 1554
- [8] VLSI design of Reed-Solomon decoder based on new architecture of modified Euclidean algorithm [J]. 2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 836 - 839
- [9] An area-efficient VLSI architecture for Reed-Solomon decoder [J]. INTERNATIONAL SYMPOSIUM ON COMMUNICATIONS AND INFORMATION TECHNOLOGIES 2005, VOLS 1 AND 2, PROCEEDINGS, 2005, : 1154 - 1158
- [10] A VLSI architecture for cellular automata based Reed-Solomon decoder [J]. FOURTH INTERNATIONAL SYMPOSIUM ON PARALLEL ARCHITECTURES, ALGORITHMS, AND NETWORKS (I-SPAN'99), PROCEEDINGS, 1999, : 158 - 165