VLSI design of Reed-Solomon decoder based on new architecture of modified Euclidean algorithm

被引：0
|
作者：
Zeng, XY [1 ]
Gu, ZY [1 ]
Chen, C [1 ]
Zhang, QL [1 ]
机构：
[1] Fudan Univ, ASIC & Syst State Key Lab, Shanghai 200433, Peoples R China
来源：
2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2003年
关键词：
D O I：
10.1109/ICASIC.2003.1277340
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A RS(255, 223) decoder based on Modified Euclidean (mE) algorithm is implented. A new VLSI architecture of the error-locator and error-evaluator module for mE algorithm is studied. The new architecture can reduce the complexity of the module and the error-probabillty of the decoder is cut-down also. The RS decoder is implemented using 0.35mum CMOS technology. and the chip-area is about 30,000 gates. system clock is 65MHz throughout is about 500Mbits/s. The decoder has the merits of low latency, low complexity and moderate throughout of data.
引用
收藏
页码：836 / 839
页数：4
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