A VLSI DESIGN OF A PIPELINE REED-SOLOMON DECODER

被引：0
|
作者：
SHAO, HM [1 ]
TRUONG, TK [1 ]
DEUTSCH, LJ [1 ]
YUEN, JH [1 ]
REED, IS [1 ]
机构：
[1] UNIV SO CALIF,DEPT ELECT ENGN,LOS ANGELES,CA 90089
来源：
IEEE TRANSACTIONS ON COMPUTERS | 1985年 / 34卷 / 05期
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：393 / 403
页数：11
相关论文
共 50 条
  • [1] ON THE VLSI DESIGN OF A PIPELINE REED-SOLOMON DECODER USING SYSTOLIC ARRAYS
    SHAO, HM
    REED, IS
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1988, 37 (10) : 1273 - 1280
  • [2] VLSI design of Reed-Solomon decoder architectures
    Lee, H
    Yu, ML
    Song, LL
    [J]. ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL V: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY, 2000, : 705 - 708
  • [3] A VLSI design for universal Reed-Solomon erasure decoder
    Xu, YS
    Zhang, TT
    [J]. 2002 6TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING PROCEEDINGS, VOLS I AND II, 2002, : 398 - 401
  • [4] VLSI Architecture for Reed-Solomon Decoder
    Kumar, A. T. Rajesh
    Rao, A. Sarveswara
    Kumar, Ratna K., V
    [J]. JOURNAL OF SPACECRAFT TECHNOLOGY, 2011, 21 (02): : 1 - 11
  • [5] A VLSI design of a high-speed Reed-Solomon decoder
    Lee, HH
    [J]. 14TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2001, : 316 - 320
  • [6] A VLSI design of Reed-Solomon Decoder for IEEE 802.16d
    Shen, Qian
    Lin, Pin
    [J]. IC-BNMT 2007: Proceedings of 2007 International Conference on Broadband Network & Multimedia Technology, 2007, : 1 - 4
  • [7] A VLSI design of a pipelining and area-efficient Reed-solomon decoder
    Wang, Wei-min
    Bi, Du-yan
    Du, Xing-min
    Ma, Lin-hua
    [J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2007, E90D (08) : 1301 - 1303
  • [8] Area-efficient VLSI design of Reed-Solomon decoder for HDTV
    Information Engineering School, Beijing University of Science and Technology, Beijing 100083, China
    [J]. Jisuanji Gongcheng, 2006, 16 (11-13+28):
  • [9] An efficient Reed-Solomon decoder VLSI with erasure correction
    Oh, K
    Sung, WY
    [J]. SIPS 97 - 1997 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: DESIGN AND IMPLEMENTATION, 1997, : 193 - 201
  • [10] A Low Complexity VLSI Architecture for Reed-Solomon Decoder
    Khalesi, Hasan
    Nabavi, A.
    Bornoosh, B.
    [J]. ICSPC: 2007 IEEE INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND COMMUNICATIONS, VOLS 1-3, PROCEEDINGS, 2007, : 1551 - 1554
12345