Impact of power-supply noise on timing in high-frequency microprocessors

This paper analyses the impact of power-supply noise on the performance of high-frequency microprocessors. First, a delay model that takes this noise into account is proposed for device-dominated and interconnect-dominated timing paths. then, realistic values for the model parameters are measured on a 2.53-GHz Pentium(R) 4 microprocessor. These values imply that the power-supply noise present on the system board currently reduces clock frequency by 6.5%. The model suggests that the frequency penalty associated with this power-supply noise will reach 8.0% for the 90-nm technology generation.