Stencil mask ion implantation technology for realistic approach to wafer process

被引：0
|
作者：
Tonari, Kazuhiko [1 ]
Nishihashi, Tsutomu [1 ]
Ishikawa, Michio [1 ]
Fujiyama, Junki [1 ]
机构：
[1] Ulvac Inc, 1220-1 Suyama, Susono, Shizuoka 2101231, Japan
来源：
ION IMPLANTATION TECHNOLOGY | 2006年 / 866卷
关键词：
stencil mask; ion implanter; stencil mask ion implanter; agile-fab; mini-fab;
D O I：
暂无
中图分类号：
O59 [应用物理学];
学科分类号：
摘要：
We are researching and developing the stencil mask ion implanter (SLIM), which enables direct implantation on wafer through a stencil mask. This technology eliminates photo resist lithography processes for ion implantation. The basic performances of SLIM as an ion implanter were the same level as those of conventional ion implanters. "SLIM process" has an effect of shortening the process time to 1/4. We present the solution to magnification alignment error, and also introduce three examples of applying this process: reduction of the threshold voltage errors, formation of ring ion implantation area and formation of isolated diffusion layer.
引用
收藏
页码：401 / +
页数：2
相关论文
共 50 条
  • [1] Stencil mask ion implantation technology
    Shibata, T
    Suguro, K
    Sugihara, K
    Nishihashi, T
    Fujiyama, J
    Sakurada, Y
    [J]. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2002, 15 (02) : 183 - 188
  • [2] Application of stencil mask ion implantation technology to power semiconductors
    Nishiwaki, T.
    Saito, H.
    Hamada, K.
    Tonari, K.
    Nishihashi, T.
    [J]. ION IMPLANTATION TECHNOLOGY, 2006, 866 : 357 - +
  • [3] Stencil mask ion implantation technology for high performance MOSFETs.
    Shibata, T
    Suguro, K
    Sugihara, K
    Mizuno, H
    Yagishita, A
    Saito, T
    Okumura, K
    Nishihashi, T
    Gotou, T
    Tsunoda, M
    Saji, S
    [J]. INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, : 869 - 871
  • [4] SOI wafer flow process for stencil mask fabrication
    Butschke, J
    Ehrmann, A
    Höfflinger, B
    Irmscher, M
    Käsmaier, R
    Letzkus, F
    Löschner, H
    Mathuni, J
    Reuter, C
    Schomburg, C
    Springer, R
    [J]. MICROELECTRONIC ENGINEERING, 1999, 46 (1-4) : 473 - 476
  • [5] Stencil mask technology for ion beam lithography
    Ehrmann, A
    Huber, S
    Käsmaier, R
    Oelmann, A
    Struck, T
    Springer, R
    Butschke, J
    Letzkus, F
    Kragler, K
    Löschner, H
    Rangelow, I
    [J]. 18TH ANNUAL SYMPOSIUM ON PHOTOMASK TECHNOLOGY AND MANAGEMENT, 1998, 3546 : 194 - 205
  • [6] PN and SOI wafer flow process for stencil mask fabrication
    Butschke, J
    Ehrmann, A
    Haugeneder, E
    Irmscher, M
    Käsmaier, R
    Kragler, K
    Letzkus, F
    Löschner, H
    Mathuni, J
    Rangelow, IW
    Reuter, C
    Shi, F
    Springer, R
    [J]. 15TH EUROPEAN CONFERENCE ON MASK TECHNOLOGY FOR INTEGRATED CIRCUITS AND MICROCOMPONENTS '98, 1999, 3665 : 20 - 29
  • [7] Progress in placement central for ion beam stencil mask technology
    Kamm, FM
    Ehrmann, A
    Struck, T
    Kragler, K
    Butschke, J
    Letzkus, F
    Springer, R
    Haugeneder, E
    Degen, A
    Voigt, J
    Kratzenberg, M
    Rangelow, IW
    [J]. 17TH EUROPEAN CONFERENCE ON MASK TECHNOLOGY FOR INTEGRATED CIRCUITS AND MICROCOMPONENTS, 2001, 4349 : 18 - 22
  • [8] Progress in placement control for ion beam stencil mask technology
    Kamm, FM
    Ehrmann, A
    Struck, T
    Kragler, K
    Butschke, J
    Letzkus, F
    Springer, R
    Haugeneder, E
    [J]. EMERGING LITHOGRAPHIC TECHNOLOGIES V, 2001, 4343 : 460 - 465
  • [9] Dry etch improvements in the SOI Wafer Flow Process for IPL stencil mask fabrication
    Letzkus, F
    Butschke, J
    Höfflinger, B
    Irmscher, M
    Reuter, C
    Springer, R
    Ehrmann, A
    Mathuni, J
    [J]. MICROELECTRONIC ENGINEERING, 2000, 53 (1-4) : 609 - 612
  • [10] Stencil technology for wafer level bumping
    Kay, Robert W.
    Cummins, Gerard
    Desmulliez, Marc P. Y.
    Krebs, Thomas
    Lathrop, Richard
    [J]. 2012 4TH ELECTRONIC SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE (ESTC), 2012,
12345