共 48 条
- [2] PN and SOI wafer flow process for stencil mask fabrication [J]. 15TH EUROPEAN CONFERENCE ON MASK TECHNOLOGY FOR INTEGRATED CIRCUITS AND MICROCOMPONENTS '98, 1999, 3665 : 20 - 29
- [3] p-n junction-based wafer flow process for stencil mask fabrication [J]. JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1998, 16 (06): : 3592 - 3598
- [4] Dry etch proximity modeling in mask fabrication [J]. PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY X, 2003, 5130 : 86 - 91
- [5] Analysis of dry etch loading effect in mask fabrication [J]. 21ST ANNUAL BACUS SYMPOSIUM ON PHOTOMASK TECHNOLOGY, PTS 1 AND 2, 2002, 4562 : 609 - 615
- [6] 200-mm EPL stencil mask fabrication by using SOI substrate [J]. PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY X, 2003, 5130 : 925 - 933
- [7] Stencil mask ion implantation technology for realistic approach to wafer process [J]. ION IMPLANTATION TECHNOLOGY, 2006, 866 : 401 - +
- [8] Stencil mask fabrication for cell projection e-Beam lithography with silicon wafer [J]. PHOTOMASK AND X-RAY MASK TECHNOLOGY VI, 1999, 3748 : 486 - 494
- [9] Mask CD correction method using dry etch process [J]. PHOTOMASK TECHNOLOGY 2006, PTS 1 AND 2, 2006, 6349
- [10] MEMS process flow insensitive to timed etch induced anchor perimeter variation on SOI and bulk silicon wafer substrates [J]. TRANSDUCERS '07 & EUROSENSORS XXI, DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2, 2007,