Dry etch improvements in the SOI Wafer Flow Process for IPL stencil mask fabrication

被引:27
|
作者
Letzkus, F
Butschke, J
Höfflinger, B
Irmscher, M
Reuter, C
Springer, R
Ehrmann, A
Mathuni, J
机构
[1] Inst Mikroelekt Stuttgart, D-70569 Stuttgart, Germany
[2] Infineon Technol AG, D-81617 Munich, Germany
关键词
D O I
10.1016/S0167-9317(00)00388-9
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The 4x Ion Projection Lithography (IPL), which is designed to reach sub 100nm resolution on the wafer plane, uses stencil membrane masks out of 150mm SOI (Silicon On Insulator) wafers [1]. The structured circular membranes have a diameter of 126mm and a thickness of 3 mu m. Results of a new sub-quarter micron trench etch and membrane dry etch process are presented and discussed.
引用
收藏
页码:609 / 612
页数:4
相关论文
共 48 条
  • [1] SOI wafer flow process for stencil mask fabrication
    Butschke, J
    Ehrmann, A
    Höfflinger, B
    Irmscher, M
    Käsmaier, R
    Letzkus, F
    Löschner, H
    Mathuni, J
    Reuter, C
    Schomburg, C
    Springer, R
    [J]. MICROELECTRONIC ENGINEERING, 1999, 46 (1-4) : 473 - 476
  • [2] PN and SOI wafer flow process for stencil mask fabrication
    Butschke, J
    Ehrmann, A
    Haugeneder, E
    Irmscher, M
    Käsmaier, R
    Kragler, K
    Letzkus, F
    Löschner, H
    Mathuni, J
    Rangelow, IW
    Reuter, C
    Shi, F
    Springer, R
    [J]. 15TH EUROPEAN CONFERENCE ON MASK TECHNOLOGY FOR INTEGRATED CIRCUITS AND MICROCOMPONENTS '98, 1999, 3665 : 20 - 29
  • [3] p-n junction-based wafer flow process for stencil mask fabrication
    Rangelow, IW
    Shi, F
    Volland, B
    Sossna, E
    Petrashenko, A
    Hudek, P
    Sunyk, R
    Butschke, J
    Letzkus, F
    Springer, R
    Ehrmann, A
    Gross, G
    Kaesmaier, R
    Oelmann, A
    Struck, T
    Unger, G
    Chalupka, A
    Haugeneder, E
    Lammer, G
    Löschner, H
    Tejeda, R
    Lovell, E
    Engelstad, R
    [J]. JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1998, 16 (06): : 3592 - 3598
  • [4] Dry etch proximity modeling in mask fabrication
    Granik, Y
    [J]. PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY X, 2003, 5130 : 86 - 91
  • [5] Analysis of dry etch loading effect in mask fabrication
    Lee, JY
    Cho, SY
    Kim, CH
    Lee, SW
    Choi, SW
    Han, WS
    Sohn, JM
    [J]. 21ST ANNUAL BACUS SYMPOSIUM ON PHOTOMASK TECHNOLOGY, PTS 1 AND 2, 2002, 4562 : 609 - 615
  • [6] 200-mm EPL stencil mask fabrication by using SOI substrate
    Sugimura, H
    Eguchi, H
    Yoshii, T
    Tamura, A
    [J]. PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY X, 2003, 5130 : 925 - 933
  • [7] Stencil mask ion implantation technology for realistic approach to wafer process
    Tonari, Kazuhiko
    Nishihashi, Tsutomu
    Ishikawa, Michio
    Fujiyama, Junki
    [J]. ION IMPLANTATION TECHNOLOGY, 2006, 866 : 401 - +
  • [8] Stencil mask fabrication for cell projection e-Beam lithography with silicon wafer
    Choi, JS
    Yi, SH
    Choi, YY
    Huh, H
    Kim, J
    [J]. PHOTOMASK AND X-RAY MASK TECHNOLOGY VI, 1999, 3748 : 486 - 494
  • [9] Mask CD correction method using dry etch process
    Jung, Ho Yong
    Ha, Tae Joong
    Shin, Jae Cheon
    Jeong, Ku Cheol
    Kim, Young Kee
    Han, Oscar
    [J]. PHOTOMASK TECHNOLOGY 2006, PTS 1 AND 2, 2006, 6349
  • [10] MEMS process flow insensitive to timed etch induced anchor perimeter variation on SOI and bulk silicon wafer substrates
    O'Brien, C. J.
    Monk, D. J.
    [J]. TRANSDUCERS '07 & EUROSENSORS XXI, DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2, 2007,