A Current-Mode Flash ADC for Low-Power Continuous-Time Sigma Delta Modulators

被引：0

作者：

Park, Chang-Joon ^{[1
]}

Geddada, Hemasundar Mohan ^{[1
]}

Karsilayan, Aydin Ilker ^{[1
]}

Silva-Martinez, Jose ^{[1
]}

Onabajo, Marvin ^{[2
]}

机构：

[1] Texas A&M Univ, Dept Elect & Comp Engn, College Stn, TX 77843 USA

[2] Northeastern Univ, Dept Elect & Comp Engn, Boston, MA 02115 USA

来源：

2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2013年

关键词：

CMOS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A current-mode flash analog-to-digital converter (ADC) with current summing stage was designed and evaluated. The topology is intended for low-power feed-forward continuous-time sigma delta (CTSD) modulators and was fabricated in a commercial 90nm CMOS technology. A 3-bit prototype has an effective number of bits (ENOB) of 2.87 bits at 2GS/s with 12MHz full-range input power. The static DNL and INL errors are both in the range of 0.24 LSB. The ADC achieves an SNDR of 15dB with a 1GHz input signal and an SNDR above 19dB for input signals below 300MHz. A major advantage of this architecture is its voltage scalability as well as the reduced input capacitance. The proposed ADC core dissipates 3.1mW power from a 1.2V supply while operating at 2GHz.

引用

页码：141 / 144

页数：4

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