A 1.2V 500MHz 32-bit carry-lookahead adder

被引:0
|
作者
Cheng, KH [1 ]
Lee, WS [1 ]
Huang, YC [1 ]
机构
[1] Tamkang Univ, Dept Elect Engn, Taipei, Taiwan
关键词
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
In this paper a 1.2V 32-bit carry lookahead adder is proposed for high speed, low voltage applications. The proposed new 32-bit adder uses Non-full Voltage Swing True-Single-Phase- Clocking Logic (NSTSPC) to implement the proposed carry lookahead adder. Because the internal node of NSTSPC was non-full swing, its operation speed would be higher than the conventional TSPC. Moreover, the supply voltage for the new adder is 1.2V, thus the power dissipation would also be reduced. The 32-bit CLA adder using 0.35um 1P4M CMOS technology with 1.2V power supply could be operated on 500MHz clock frequency.
引用
收藏
页码:765 / 768
页数:4
相关论文
共 35 条
  • [1] An improved 32-bit Carry-Lookahead Adder with Conditional Carry-Selection
    Chen Ping-hua
    Zhao Juan
    Xie Guo-bo
    Li Yi-jun
    [J]. ICCSSE 2009: PROCEEDINGS OF 2009 4TH INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE & EDUCATION, 2009, : 1911 - 1913
  • [2] A 3.5 NS, 64 BIT, carry-lookahead adder
    Dozza, D
    Gaddoni, M
    Baccarani, G
    [J]. ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 2, 1996, : 297 - 300
  • [3] A structured approach for optimizing 4-bit carry-lookahead adder
    Institute of Micro-Nano Electronic Systems, Ningbo University, Zhejiang
    315211, China
    不详
    315211, China
    [J]. Open Electr. Electron. Eng. J., 1 (133-142):
  • [4] A structured approach for optimizing 4-bit carry-lookahead adder
    Cheng, Wei
    Hu, Jianping
    [J]. Open Electrical and Electronic Engineering Journal, 2014, 8 (01): : 133 - 142
  • [5] A 32-bit carry lookahead adder using dual-path all-N logic
    Yang, G
    Jung, SO
    Baek, KH
    Kim, SH
    Kim, S
    Kang, SM
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2005, 13 (08) : 992 - 996
  • [6] A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic
    Wang, CC
    Tseng, YL
    Lee, PM
    Lee, RC
    Huang, CJ
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS, 2003, 50 (09): : 1208 - 1216
  • [7] Application of logical effort on delay analysis of 64-bit static carry-lookahead adder
    Dao, HQ
    Oklobdzija, VG
    [J]. CONFERENCE RECORD OF THE THIRTY-FIFTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, VOLS 1 AND 2, 2001, : 1322 - 1324
  • [8] A 32-Bit Ripple-Ling Hybrid Carry Adder
    Shang, Ning
    Wang, Zhou
    Liu, Ruikang
    Huang, Yizhou
    Zhang, Yin
    He, Zhangqing
    Wan, Meilin
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2024, 71 (06) : 2709 - 2722
  • [9] Numerical Model for 32-Bit Magnonic Ripple Carry Adder
    Garlando, Umberto
    Wang, Qi
    Dobrovolskiy, Oleksandr V.
    Chumak, Andrii V.
    Riente, Fabrizio
    [J]. IEEE Transactions on Emerging Topics in Computing, 2023, 11 (03): : 679 - 688
  • [10] Delay Efficient 32-Bit Carry-Skip Adder
    Lin, Yu Shen
    Radhakrishnan, Damu
    [J]. VLSI DESIGN, 2008,