共 35 条
- [1] An improved 32-bit Carry-Lookahead Adder with Conditional Carry-Selection [J]. ICCSSE 2009: PROCEEDINGS OF 2009 4TH INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE & EDUCATION, 2009, : 1911 - 1913
- [2] A 3.5 NS, 64 BIT, carry-lookahead adder [J]. ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 2, 1996, : 297 - 300
- [3] A structured approach for optimizing 4-bit carry-lookahead adder [J]. Open Electr. Electron. Eng. J., 1 (133-142):
- [4] A structured approach for optimizing 4-bit carry-lookahead adder [J]. Open Electrical and Electronic Engineering Journal, 2014, 8 (01): : 133 - 142
- [6] A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS, 2003, 50 (09): : 1208 - 1216
- [7] Application of logical effort on delay analysis of 64-bit static carry-lookahead adder [J]. CONFERENCE RECORD OF THE THIRTY-FIFTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, VOLS 1 AND 2, 2001, : 1322 - 1324
- [9] Numerical Model for 32-Bit Magnonic Ripple Carry Adder [J]. IEEE Transactions on Emerging Topics in Computing, 2023, 11 (03): : 679 - 688