On the universality of drain-induced-barrier-lowering in field-effect transistors

In this paper, we revisit on the extraction of drain-induced-barrier-lowering (DIBL) in various types of field-effect transistors (FETs) with L-g ranging from several mu m to sub-30 nm and from planar to gate-all-around (GAA) architectures, aiming to unify the extraction methodology of DIBL. In doing so, we found that the values of DIBL extracted in the conventional manner were strongly dependent on the choice of V-DS in the linear regime, especially for V-DS < 4x(kT/q). To physically understand this, we constructed a first-order model for the threshold voltage (V-T), which explains the abnormal positive shift of V-T with V-DS for V-DS < 4x(kT/q). This additional positive shift of V-T in the linear regime resulted in overestimation of DIBL. In an effort to unify the extraction procedure of DIBL, we herein propose first how to accurately extract DIBL and then how to correct reported values of DIBL extracted in the conventional manner. Finally, we highlighted the importance of accurate extraction of DIBL from the viewpoint of its impact on virtual-source modeling, universal relationship between DIBL and aspect ratio, and projection of maximum oscillation frequency (f(max)).