共 50 条
- [43] Path delay test generation for domino logic circuits in the presence of crosstalk INTERNATIONAL TEST CONFERENCE 2003, PROCEEDINGS, 2003, : 122 - 130
- [44] A Novel Leakage Reduction DOIND Approach For Nanoscale Domino Logic Circuits 2015 EIGHTH INTERNATIONAL CONFERENCE ON CONTEMPORARY COMPUTING (IC3), 2015, : 434 - 438
- [46] On an Interactive Optimization Method for the Design of Integrated Circuits. AEU. Archiv fur Elektronik und Ubertragungstechnik, 1986, 40 (01): : 1 - 9
- [49] A technique for designing totally self-checking domino logic circuits 6TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2005, : 128 - 132
- [50] ON AN INTERACTIVE OPTIMIZATION METHOD FOR THE DESIGN OF INTEGRATED-CIRCUITS AEU-ARCHIV FUR ELEKTRONIK UND UBERTRAGUNGSTECHNIK-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 1986, 40 (01): : 1 - 9