100 Gbit/s fully integrated InP DHBT-based CDR/1:2 DEMUX IC

被引:0
|
作者
Makon, R. E. [1 ]
Driad, R. [1 ]
Loesch, R. [1 ]
Rosenzweig, J. [1 ]
Schlechtweg, M. [1 ]
机构
[1] Fraunhofer Inst Appl Solid State Phys, IAF, D-79108 Freiburg, Germany
来源
关键词
InP double heterostructure bipolar transistor (DHBT); integrated circuit (IC); clock and data recovery (CDR); half-rate linear phase detector; demultiplexer (DEMUX); loop filter; voltage controlled oscillator (VCO);
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, a 100 Gbit/s fully integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX) is presented. The integrated circuit (IC) is realized using an in-house InP double heterostructure bipolar transistor (DHBT) technology exhibiting cut-off frequency values of more than 300 GHz for both f(T) and f(max). The CDR IC consists mainly of a half-rate linear phase detector including a 1:2 DEMUX, a loop filter, and a voltage controlled oscillator (VCO). A 100 Gbit/s data signal at the corresponding input of the CDR circuit gives rise to 50 Gbit/s recovered and demultiplexed output data featuring clear eye opening and a voltage swing of 500 mV(pp). The extracted 50 GHz clock signal from the input data features a voltage swing of 250 mV(pp), while the corresponding peak-to-peak (pp) and rms jitter amount to 2.1 ps and 0.5 ps, respectively. The full IC dissipates 2.1 W at a single supply voltage of -4.5 V.
引用
收藏
页码:124 / 127
页数:4
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