Design for testability: Tunnelling through the test wall

被引：0
|
作者：
Maxwell, PC
机构：
来源：
PROCEEDINGS OF THE IEEE 1997 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 1997年
关键词：
D O I：
10.1109/CICC.1997.606613
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper discusses design for testability as a means of ensuring that high quality tests can be generated for an IC in reasonable time by avoiding the ''over the wall'' mentality. A discussion on fault models is followed by general benefits of DFT. Scan design is then described in some detail, together with general DFT guidelines, including representative design rules which must be followed. Some cost/benefit tradeoffs are considered, and the paper concludes by discussing various required components of a composite test suite.
引用
收藏
页码：199 / 206
页数：8
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