Design for testability: Tunnelling through the test wall

This paper discusses design for testability as a means of ensuring that high quality tests can be generated for an IC in reasonable time by avoiding the ''over the wall'' mentality. A discussion on fault models is followed by general benefits of DFT. Scan design is then described in some detail, together with general DFT guidelines, including representative design rules which must be followed. Some cost/benefit tradeoffs are considered, and the paper concludes by discussing various required components of a composite test suite.