High Order Single-bit Delta Sigma Modulator for Fractional-N Frequency Synthesis in Multi-Standard Transceiver

被引：0
|
作者：
Abeda, Aymen [1 ]
Ben-Romdhane, Manel [1 ]
Rebai, Chiheb [1 ]
机构：
[1] Ecole Super Commun Tunis SUPCOM, CIRTACOM Res Lab, Ariana, Tunisia
来源：
SCS: 2008 2ND INTERNATIONAL CONFERENCE ON SIGNALS, CIRCUITS AND SYSTEMS | 2008年
关键词：
Multi-standard frequency synthesis; Fractional-N PLL; Digital Delta Sigma modulator;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper proposes a new stable design strategy for 1-bit high order digital Delta Sigma modulator used as division controller for multi-standard fractional-N frequency synthesizer. This digital Delta Sigma modulator presents simplicity and low power consumption. Simulation results illustrate the Delta Sigma modulator good performances in terms of spectrum purity and accuracy.
引用
收藏
页码：337 / 342
页数：6
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