A Family of Modular Area- and Energy-Efficient QRD-Accelerator Architectures

被引：0

作者：

Vishnoi, Upasna ^{[1
]}

Noll, Tobias G. ^{[1
]}

机构：

[1] Rhein Westfal TH Aachen, Chair Elect Engn & Comp Syst, Aachen, Germany

来源：

INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP (SOC) | 2013年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

QR-decomposition accelerators are attractive SoC components for many applications with a wide range of specifications. A new family of highly area- and energy-efficient, modular two-way linear-array QRD architectures based on the Givens algorithm and CORDIC rotations is proposed. The template architecture allows for implementations of real-/complex-valued and integer/floating-point QRDs. An accurate algebraic cost model enables cross-level optimization over architecture, micro-architecture and circuit level using a rich set of parameters. Quantitative results for exemplary applications are presented for implementations in 40-nm CMOS, proving the significant improvement of efficiency.

引用

页数：8

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