Power Delivery Network Design and Modeling for High Bandwidth Memory (HBM)

被引：0
|
作者：
Shi, Wenjun [1 ]
Zhou, Yaping [1 ]
Sudhakaran, Sunil [1 ]
机构：
[1] NVIDIA Corp, Santa Clara, CA 95050 USA
来源：
2016 IEEE 25TH CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS) | 2016年
关键词：
High Bandwidth Memory; simultanuous switching noise; power supply induced jitter;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A modeling method to consider simulation switching noise of HBM and its impact on HBM timing is described. This method combines partial element equivalent circuit model for power delivery network and S-parameters based HBM channel model together in HBM studies.
引用
收藏
页码：3 / 5
页数：3
相关论文
共 50 条
  • [31] A Novel Through Mold Plate (TMP) for Signal and Thermal Integrity Improvement of High Bandwidth Memory (HBM)
    Son, Keeyoung
    Kim, Subin
    Park, Hyunwook
    Kim, Seongguk
    Kim, Keunwoo
    Park, Shinyoung
    Sim, Boogyo
    Jeong, Seungtaek
    Park, Gapyeol
    Kim, Joungho
    2020 IEEE MTT-S INTERNATIONAL CONFERENCE ON NUMERICAL ELECTROMAGNETIC AND MULTIPHYSICS MODELING AND OPTIMIZATION (NEMO 2020), 2020,
  • [32] Design of Power Delivery Network Droops
    Yang, Long
    2021 JOINT IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, SIGNAL & POWER INTEGRITY, AND EMC EUROPE (EMC+SIPI AND EMC EUROPE), 2021, : 959 - 962
  • [33] Low Temperature SoIC™ Bonding and Stacking Technology for 12/16-Hi High Bandwidth Memory (HBM)
    Tsai, C. H.
    Ku, Terry
    Chen, M. F.
    Chiou, W. C.
    Wang, C. T.
    Yu, Douglas
    2020 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, 2020,
  • [34] Characterization and modeling of the power delivery networks of memory chips
    Stievano, I. S.
    Maio, I. A.
    Rigazio, L.
    Canavero, F. G.
    Izzi, R.
    Girardi, A.
    Lessio, T.
    Conci, A.
    Cunha, T.
    Teixeira, H.
    Pedro, J. C.
    2009 IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS, 2009, : 5 - +
  • [35] Multilayer power delivery network design for high-speed microprocessor system
    Park, SG
    Kim, J
    Yook, JG
    Park, HK
    53RD ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2003 PROCEEDINGS, 2003, : 1613 - 1618
  • [36] Power Delivery Network Design Strategy for Next Generation High Speed IO
    Moorthy, Mukesh
    Jayasimha, Manjunath
    2018 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS 2018), 2018,
  • [37] Low Temperature SoIC Bonding and Stacking Technology for 12-/16-Hi High Bandwidth Memory (HBM)
    Chen, M. F.
    Tsai, C. H.
    Ku, Terry
    Chiou, W. C.
    Wang, C. T.
    Yu, Douglas
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (12) : 5343 - 5348
  • [38] Overcoming Design Challenges for High Bandwidth Memory Interface with CoWoS
    Chen, Victor
    Abdel-dayem, Bassem
    Wan, Changhua
    Ling, Feng
    2022 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY & SIGNAL/POWER INTEGRITY, EMCSI, 2022, : 455 - 458
  • [39] Inverse design of high efficiency and large bandwidth power splitter for arbitrary power ratio based on deep residual network
    Jin Wen
    Zhengwei Wu
    Hui Zhang
    Qian Wang
    Huimin Yu
    Ying Zhang
    Yu Pan
    Zhanzhi Liu
    Optical and Quantum Electronics, 56
  • [40] Modeling the network processor and package for power delivery analysis
    Cui, W
    Parmar, P
    Morgan, JM
    Sheth, U
    EMC 2005: IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, VOLS 1-3, PROCEEDINGS, 2005, : 690 - 694
12345