共 50 条
- [42] A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs IEEE Transactions on Circuits and Systems II: Express Briefs, 2016, 63 (06): : 518 - 522
- [44] An Extensible FPGA-based Postprocessor Architecture of Timing Skew Correction for Time-Interleaved ADCs 2012 5TH INTERNATIONAL CONGRESS ON IMAGE AND SIGNAL PROCESSING (CISP), 2012, : 1426 - 1429
- [46] Difference-equalisation based estimation of timing skew for time-interleaved ADCs in communication systems Electronics Letters, 2019, 55 (25): : 1326 - 1329
- [47] A simple, digital method for background estimation of timing mismatches in time-interleaved ADCs PRZEGLAD ELEKTROTECHNICZNY, 2022, 98 (09): : 174 - 177
- [50] Blind Adaptive Calibration of Timing Error for Two-Channel Time-Interleaved ADCs 53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 233 - 236