A Low-Power Area-Efficient Compressive Sensing Approach for Multi-Channel Neural Recording

被引:0
|
作者
Shoaran, Mahsa [1 ]
Lopez, Mariazel Maqueda [1 ]
Pasupureddi, Vijaya Sankara Rao [1 ]
Leblebici, Yusuf [1 ]
Schmid, Alexandre [1 ]
机构
[1] Ecole Polytech Fed Lausanne, Swiss Fed Inst Technol, Microelect Syst Lab LSM, CH-1015 Lausanne, Switzerland
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
High-density wireless intracranial neural recording is a promising technology enabling the autonomous diagnosis and therapy of brain diseases. Increasing the number of recording channels is accompanied by the increased amount of data resulting in an unacceptable transmission power. A comprehensive study of possible compressed sensing methods in the context of neural signals has been done, and the compression of signals originating from different channels in the spatial domain has been implemented at the system and circuit levels. Results of the simulations in a UMC 0.18 mu m CMOS technology and subsequent reconstructions show the possibility of compressing with ratios as high as 2.6 with a recovery SNR of at least 10dB using extremely compact and low-power circuits. The power efficiency and limited area per channel confirm the relevance of the proposed approach for multi-channel high-density neural interfaces.
引用
收藏
页码:2191 / 2194
页数:4
相关论文
共 50 条
  • [31] Pre-charge solution for low-power, area-efficient SAR ADC
    Sarafi, Sahar
    Bin Aain, Abu Khari
    Bargoshadi, Javad Abbaszadeh
    Chegini, Amin
    IEICE ELECTRONICS EXPRESS, 2015, 12 (20):
  • [32] Low-power and area-efficient FIR filter implementation suitable for multiple taps
    Kim, KS
    Lee, K
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2003, 11 (01) : 150 - 153
  • [33] An area-efficient low-power SC integrator for very high resolution ADCS
    Zare-Hoseini, H
    Azizi, MY
    Shoaei, O
    SCS 2003: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS, 2003, : 365 - 368
  • [34] A low-power and area-efficient quaternary adder based on CNTFET switching logic
    Shirin Fakhari
    Narges Hajizadeh Bastani
    Mohammad Hossein Moaiyeri
    Analog Integrated Circuits and Signal Processing, 2019, 98 : 221 - 232
  • [35] Low-power area-efficient decimation filters in sigma-delta ADCs
    Yi, Feng
    Wu, Xiaobo
    Xu, Jian
    EDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGS, 2007, : 833 - 836
  • [36] Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier
    Shrestha, Rahul
    Rastogim, Utkarsh
    2016 29TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2016 15TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID), 2016, : 599 - 600
  • [37] A Low-Power Area-Efficient 8 bit SAR ADC Using Dual Capacitor Arrays for Neural Microsystems
    Chang, Sun-Il
    Yoon, Euisik
    2009 ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY, VOLS 1-20, 2009, : 1647 - 1650
  • [38] Multi-Channel Neural Recording Implants: A Review
    Noshahr, Fereidoon Hashemi
    Nabavi, Morteza
    Sawan, Mohamad
    SENSORS, 2020, 20 (03)
  • [39] Robust hyperspectral reconstruction via a multi-channel clustering compressive sensing approach
    Gu, Yan-Da
    Liu, Xing-Ling
    Li, Yu-Hang
    Chu, Jun-Qiu
    Ma, Hao-Tong
    OPTICS AND LASERS IN ENGINEERING, 2024, 183
  • [40] The Design of 8-Channel CMOS Area-Efficient Low-Power Current-Mode Analog Front-End Amplifier for EEG Signal Recording
    Sung, Ya-Syuan
    Chen, Wei-Ming
    Wu, Chung-Yu
    2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2016, : 530 - 533