Least squares approximation-based ROM-free direct digital frequency synthesizer

被引：0

作者：

Wen, CH ^{[1
]}

Hsu, HY ^{[1
]}

Ko, HY ^{[1
]}

Wu, AY ^{[1
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 106, Taiwan

来源：

2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper describes a new design approach and an architecture for a Direct Digital Frequency Synthesizer (DDFS) based on Least Square (LS) approximation. It is shown that the architecture can be implemented as a low-cost, low-power, feedforward, and easily pipelineable datapath. A prototype IC has been designed and fabricated in TSMC 0.25 um CMOS technology. The IC produces 14-bit sine and cosine outputs with a spurious free dynamic range of 100 dBc. A 32-bit frequency word gives a tuning resolution of 0.0466 Hz at 200 MHz sampling rate.

引用

页码：701 / 704

页数：4

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