Modeling techniques and tests for partial faults in memory devices

被引：1

作者：

Al-Ars, Z ^{[1
]}

van de Goor, AJ ^{[1
]}

机构：

[1] Delft Univ Technol, Fac Informat Technol & Syst, Sect Comp Engn, NL-2628 CD Delft, Netherlands

来源：

DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2002 PROCEEDINGS | 2002年

关键词：

partial faults; DRAMs; fault models; defect simulation; memory testing; completing operations;

D O I：

10.1109/DATE.2002.998254

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

It has always been assumed that fault models in memories are sufficiently precise for specifying the faulty behavior. This means that, given a fault model, it should be possible to construct a test that ensures detecting the modeled fault. This paper shows that some faults, called partial faults, are particularly difficult to detect. For these faults, more operations are required to complete their fault effect and to ensure detection. The paper also presents fault analysis results, based on defect injection and simulation, where partialfaults have been observed. The impact of partialfaults on testing is discussed and a test to detect these partialfaults is given.

引用

页码：89 / 93

页数：5

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