Modeling Techniques for Electronic Noise and Process Variability in Nanoscale Devices

Modeling random variations in semiconductor devices becomes increasingly important since at the nanometer scale the intrinsic granularity of matter makes the use of average quantities to be affected by high uncertainty. In this paper we present a unified framework to address statistical variations of a semiconductor device performance due to both microscopic noise sources (noise analysis) and random variations of technological parameters (variability analysis), highlighting that often the two phenomena are intermixed. We present the simulation through variability analysis of Random Telegraph Noise (RTN), traced back to randomly occupied localized traps located close to the Si/ SiO2 interface, especially relevant for advanced floating gate non-volatile memories.