Low-power digital latch circuit using magnetic logic device

被引:2
|
作者
Qin, Tao [1 ]
Cai, Li [1 ]
Yang, Xiaokuo [1 ]
Zhang, Mingliang [1 ]
机构
[1] Air Force Engn Univ, Coll Sci, Xian 710051, Peoples R China
基金
中国国家自然科学基金;
关键词
DOT CELLULAR-AUTOMATA; QUANTUM;
D O I
10.1049/el.2015.2487
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The in-plane magnetic logic device is a spin-based technology which offers several advantages over charged-based devices such as non-volatility, ultra-low power and greater integration density. A novel low-power digital latch circuit is proposed by using various shaped nanomagnets. Specifically, a pipelined clocking layout is effectively constructed to ensure sequential and reliable operation. The simulation results show that the magnetic logic latch performs well. The proposed circuit is promising in building future ultra-low power magnetic memories, and may inspire new applications (i.e. magnetic arithmetic circuits).
引用
收藏
页码:1800 / 1801
页数:2
相关论文
共 50 条
  • [1] Device-Circuit Analysis of Ferroelectric FETs for Low-Power Logic
    Gupta, Shreya
    Steiner, Mark
    Aziz, Ahmedullah
    Narayanan, Vijaykrishnan
    Datta, Suman
    Gupta, Sumeet Kumar
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64 (08) : 3092 - 3100
  • [2] A Low-Power Circuit Technique for Domino CMOS Logic
    Meher, Preetisudha
    Mahapatra, K. K.
    2013 INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS AND SIGNAL PROCESSING (ISSP), 2013, : 256 - 261
  • [3] A New Low-Power CMOS Dynamic Logic Circuit
    Jia, Song
    Lyu, Shigong
    Meng, Qinglong
    Wu, Fengfeng
    Xu, Heqing
    2013 IEEE INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2013,
  • [4] A novel low-power logic circuit design scheme
    Starzyk, Janusz A.
    He, Haibo
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2007, 54 (02) : 176 - 180
  • [5] Low-Power Supply Circuit Using Off-Chip Resonant Circuit for Adiabatic Logic
    Takahashi, Yasuhiro
    Sato, Hisao
    ELECTRONICS AND COMMUNICATIONS IN JAPAN, 2015, 98 (03) : 1 - 8
  • [6] Low-Power Sequential Circuit Using Single Phase Adiabatic Dynamic Logic
    Chanda, M.
    Dandapat, A.
    Rahaman, H.
    2009 4TH INTERNATIONAL CONFERENCE ON COMPUTERS AND DEVICES FOR COMMUNICATION (CODEC 2009), 2009, : 53 - +
  • [7] POWER RAIL LOGIC - A LOW-POWER LOGIC STYLE FOR DIGITAL GAAS CIRCUITS
    CHANDNA, A
    BROWN, RB
    PUTTI, D
    KIBLER, CD
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1995, 30 (10) : 1096 - 1100
  • [8] Low-power and low-offset comparator using latch load
    Jung, Y.
    Lee, S.
    Chae, J.
    Temes, G. C.
    ELECTRONICS LETTERS, 2011, 47 (03) : 167 - U649
  • [9] Adiabatic differential logic for low-power digital systems
    Lo, Chun-Keung
    Chan, Philip C.H.
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1999, 46 (09): : 1245 - 1250
  • [10] An adiabatic differential logic for low-power digital systems
    Lo, CK
    Chan, PCH
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 1999, 46 (09) : 1245 - 1250