RSA acceleration with field programmable gate arrays

被引：0

作者：

Tiountchik, A

Trichina, E

机构：

[1] Natl Acad Sci Belarus, Math Inst, Minsk 220072, BELARUS

[2] Univ S Australia, Adv Comp Res Ctr, Mawson Lakes, SA 5095, Australia

来源：

INFORMATION SECURITY AND PRIVACY | 1999年 / 1587卷

关键词：

D O I：

暂无

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

An efficient implementations of modular exponentiation, i.e., the main building block in the RSA cryptographic scheme, is achieved by first designing a bit-level systolic array such that the whole procedure of modular exponentiation can be carried out entirely by a single unit without using global interconnections or memory to store intermediate results, and then mapping this design onto Xilinx XC6000 Field Programmable Gate Array.

引用

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页码：164 / 176

页数：13

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