A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist

被引：0

作者：

Chang, Chi-Shin ^{[1
]}

Yang, Hao-, I ^{[1
]}

Liao, Wei-Nan ^{[1
]}

Lin, Yi-Wei ^{[1
]}

Lien, Nan-Chun ^{[1
]}

Chen, Chien-Hen ^{[1
]}

Chuang, Ching-Te ^{[1
]}

Hwang, Wei ^{[1
]}

Jou, Shyh-Jye ^{[1
]}

Tu, Ming-Hsien ^{[2
]}

Huang, Huan-Shun ^{[2
]}

Hu, Yong-Jyun ^{[2
]}

Kan, Paul-Sen ^{[2
]}

Cheng, Cheng-Yo ^{[2
]}

Wang, Wei-Chang ^{[2
]}

Wang, Jian-Hao ^{[2
]}

Lee, Kuen-Di ^{[2
]}

Chen, Chia-Cheng

Shih, Wei-Chiang

机构：

[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu, Taiwan

[2] Faraday Technol Corp, Hsinchu, Taiwan

来源：

2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2013年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Write-ability is further enhanced by an Adaptive Data-Aware Write-Assist (ADAWA) scheme. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 800MHz@1.2V and 25 degrees C. The measured power consumption is 23.21mW (Active)/2.42mW (Leakage) at 1.2V, TT, 25 degrees C; and 6.01mW (Active)/0.35mW (Leakage) at 0.7V, TT, 25 degrees C.

引用

页码：1468 / 1471

页数：4

共 6 条

[1] A 40nm 1.0Mb 6T Pipeline SRAM with Digital-Based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS Tracking and Adaptive Voltage Detector for Boosting Control
Liao, Wei-Nan
Lien, Nan-Chun
Chang, Chi-Shin
Chu, Li-Wei
Yang, Hao-I
Chuang, Ching-Te
Jou, Shyh-Jye
Hwang, Wei
Tu, Ming-Hsien
Huang, Huan-Shun
Wang, Jian-Hao
Kan, Paul-Sen
Hu, Yong-Jyun
2013 IEEE 26TH INTERNATIONAL SOC CONFERENCE (SOCC), 2013, : 110 - 115
[2] A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist
Lien, Nan-Chun
Chu, Li-Wei
Chen, Chien-Hen
Yang, Hao-I.
Tu, Ming-Hsien
Kan, Paul-Sen
Hu, Yong-Jyun
Chuang, Ching-Te
Jou, Shyh-Jye
Hwang, Wei
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2014, 61 (12) : 3416 - 3425
[3] Analysis of GeOI FinFET 6T SRAM Cells With Variation-Tolerant WLUD Read-Assist and TVC Write-Assist
Hu, Vita Pi-Ho
Fan, Ming-Long
Su, Pin
Chuang, Ching-Te
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 62 (06) : 1710 - 1715
[4] 40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist
Chiu, Yi-Wei
Hu, Yu-Hao
Tu, Ming-Hsien
Zhao, Jun-Kai
Chu, Yuan-Hua
Jou, Shyh-Jye
Chuang, Ching-Te
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2014, 61 (09) : 2578 - 2585
[5] A 40 nm 0.32 V 3.5 MHz 11T Single-Ended Bit-Interleaving Subthreshold SRAM with Data-Aware Write-Assist
Chiu, Yi-Wei
Hu, Yu-Hao
Tu, Ming-Hsien
Zhao, Jun-Kai
Jou, Shyh-Jye
Chuang, Ching-Te
2013 IEEE INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED), 2013, : 51 - 56
[6] A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing
Tu, Ming-Hsien
Lin, Jihi-Yu
Tsai, Ming-Chien
Lu, Chien-Yu
Lin, Yuh-Jiun
Wang, Meng-Hsueh
Huang, Huan-Shun
Lee, Kuen-Di
Shih, Wei-Chiang
Jou, Shyh-Jye
Chuang, Ching-Te
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2012, 47 (06) : 1469 - 1482

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