Through Wafer Via Technology for MEMS and 3D Integration

被引:0
|
作者
Rimskog, Magnus [1 ]
机构
[1] Silex Microsyst, San Francisco, CA 94102 USA
关键词
through silicon via; 3d interconnect; wafer level packaging; CMOS integration; interposer;
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
The Through Silicon Via (TSV) process developed by Silex offers sub 50 mu m pitch for through wafer connections in up to 600 mu m thick substrates. The via process enables MEMS designs with significantly reduced die size and true "Wafer Level Packaging" - features that are particularly important in consumer market applications. The TSV technology also enables integration of advanced interconnect functions in optical MEMS, sensors and microfluidic devices. With several companies using the process already today and a line-up of potential users, the process is becoming a standard in the MEMS industry. This paper gives a brief introduction to the via formation process and focuses in more detail on the novel solutions made available by this enabling technology
引用
收藏
页码:174 / 177
页数:4
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