Impact of Nonlinear MOS Capacitance Effect on Transient Analysis of Interposer Through-Silicon Vias

被引:0
|
作者
Zheng, J. [1 ]
Gao, X. [1 ]
Zhao, W. -S. [1 ]
Wang, G. [1 ]
机构
[1] Hangzhou Dianzi Univ, Sch Elect & Informat, Microelect CAD Ctr, Key Lab RF Circuits & Syst,Minist Educ, Hangzhou 310018, Zhejiang, Peoples R China
基金
中国国家自然科学基金;
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, the equivalent circuit model of a pair of TSVs in a passive interposer base is developed, with the nonlinear MOS capacitance effect treated appropriately. Based on the circuit model, the transient analysis of the interposer TSVs is carried out. The results would be helpful for the design and practical applications of interposer-based 2.5-D IC systems.
引用
收藏
页码:2160 / 2163
页数:4
相关论文
共 50 条
  • [21] Impact of Frequency-Dependent and Nonlinear Parameters on Transient Analysis of Through Silicon Vias Equivalent Circuit
    Piersanti, Stefano
    de Paulis, Francesco
    Orlandi, Antonio
    Fan, Jun
    IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 2015, 57 (03) : 538 - 545
  • [22] Test Structures for Characterization of Through-Silicon Vias
    Stucchi, Michele
    Perry, Daniel
    Katti, Guruprasad
    Dehaene, Wim
    Velenis, Dimitrios
    IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2012, 25 (03) : 355 - 364
  • [23] Air-Gap Through-Silicon Vias
    Huang, Cui
    Chen, Qianwen
    Wang, Zheyao
    IEEE ELECTRON DEVICE LETTERS, 2013, 34 (03) : 441 - 443
  • [24] Power Noise Isolation in a Silicon Interposer with Through Silicon Vias
    Kim, Myunghoi
    Shin, Dong-Hwan
    Um, Man-Seok
    Yom, In-Bok
    2014 IEEE 16TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2014, : 805 - 808
  • [25] Through-Silicon Vias: Drivers, Performance, and Innovations
    Thadesar, Paragkumar A.
    Gu, Xiaoxiong
    Alapati, Ramakanth
    Bakir, Muhannad S.
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2016, 6 (07): : 1009 - 1019
  • [26] Towards Ultrasonic Through-Silicon Vias (UTSV)
    Kuo, Justin
    Hoople, Jason
    Ardanuc, Serhan
    Lal, Amit
    2014 IEEE INTERNATIONAL ULTRASONICS SYMPOSIUM (IUS), 2014, : 483 - 486
  • [27] Rigorous Electrical Modeling of Through Silicon Vias (TSVs) with MOS Capacitance Effects
    Bandyopadhyay, Tapobrata
    Han, Ki Jin
    Chung, Daehyun
    Chatterjee, Ritwik
    Swaminathan, Madhavan
    Tummala, Rao
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2011, 1 (06): : 893 - 903
  • [28] RF Characterization and Modeling of Through-Silicon Vias
    Sun, X.
    Ryckaert, J.
    Van der Plas, G.
    Beyne, E.
    2013 EUROPEAN MICROELECTRONICS PACKAGING CONFERENCE (EMPC), 2013,
  • [29] Closed-Form Expression for Capacitance of Tapered Through-Silicon-Vias Considering MOS Effect
    Wang, Fengjuan
    Yang, Yintang
    Zhu, Zhangming
    Liu, Xiaoxian
    Zhang, Yan
    2013 14TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2013, : 1250 - 1254
  • [30] High frequency characterization and analysis of through silicon vias and coplanar waveguides for silicon interposer
    Wang, Huijuan
    Ren, Xiaoli
    Zhou, Jing
    Pang, Cheng
    Song, Chongsheng
    Dai, Fengwei
    Xue, Kai
    Jiang, Feng
    Yu, Daquan
    Wan, Lixi
    MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2016, 22 (02): : 337 - 347