A Low-Power VLSI architecture for Intra and Inter prediction in H.264

被引：0

作者：

Koziri, Maria G. ^{[1
]}

Stamoulis, George I. ^{[1
]}

Katsvounidis, Ioannis X.

机构：

[1] Univ Thessaloniki, Dept Comp & Commun Engn, Glavani 37, GR-38221 Bolos, Greece

来源：

PRIME 2006: 2ND CONFERENCE ON PH.D. RESEARCH IN MICROELECTRONIC AND ELECTRONICS, PROCEEDINGS | 2006年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The H.264 video coding standard can achieve considerably higher coding efficiency than previous standards. The keys to this high code efficiency are mainly the two prediction modes (Intra & Inter) provided by the standard. Unfortunately these come at a cost in considerable increased complexity at the encoder. Therefore it is of high importance to design architectures that minimize the cost of the prediction modes. One computational element that is met in both, Inter and Intra Prediction modes, is that of the Sum of Absolute Differences (SAD). In this paper we present a new algorithm that can replace SAD in the two main Prediction Modes, and which can provide a more efficient hardware implementation.

引用

页码：109 / +

页数：2

共 50 条

[1] A low-power VLSI architecture for intra prediction in H.264
Stamoulis, G
Koziri, M
Katsavounidis, I
Bellas, N
ADVANCES IN INFORMATICS, PROCEEDINGS, 2005, 3746 : 633 - 640
[2] A Low Power Architecture for H.264 Encoder in Intra Prediction Mode
Senthilkumar, G.
Hariprasath, S.
2014 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP), 2014,
[3] High performance VLSI implementation for H.264 Inter/Intra prediction
Alle, Mythri
Biswas, J.
Nandy, S. K.
ICCE: 2007 DIGEST OF TECHNICAL PAPERS INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS, 2007, : 37 - +
[4] The VLSI implementation of intra prediction in H.264/AVC
Department of Microelectronics, Peking University, Beijing 100871, China
不详
Beijing Daxue Xuebao Ziran Kexue Ban, 2008, 1 (44-48):
[5] H.264 intra prediction architecture optimization
Wang, Shao-Bo
Zhang, Xiao-Lin
Yao, Yuan
Wang, Zhe
2007 IEEE INTERNATIONAL CONFERENCE ON MULTIMEDIA AND EXPO, VOLS 1-5, 2007, : 1571 - +
[6] An Efficient VLSI Architecture for Transform-Based Intra Prediction in H.264/AVC
Lin, Heng-Yao
Wu, Kuan-Hsien
Liu, Bin-Da
Yang, Jar-Ferr
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2010, 20 (06) : 894 - 906
[7] High Profile Intra Prediction Architecture for H.264
He, Xun
Zhou, Dajiang
Zhou, Jinjia
Goto, Satoshi
2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009), 2009, : 57 - +
[8] High-Parallel Architecture for H.264/AVC Intra Prediction Implemented via VLSI
Guo, Jiefeng
Yang, Zhixin
Zheng, Jianwei
Li, Xiaochao
Guo, Donghui
2013 IEEE INTERNATIONAL CONFERENCE ON ANTI-COUNTERFEITING, SECURITY AND IDENTIFICATION (ASID), 2013,
[9] Low Power H.264/AVC Intra Prediction for Image Processing
Ren, Guo-yan
Lie, Jian-jun
FUZZY INFORMATION AND ENGINEERING, VOLUME 2, 2009, 62 : 423 - +
[10] A low-power H.264/AVC decoder
Lin, TA
Liu, TM
Lee, CY
2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-TSA-DAT), Proceedings of Technical Papers, 2005, : 283 - 286

← 1 2 3 4 5 →