Modeling of a metal-ferroelectric-semiconductor field-effect transistor NAND gate

The modeling of a NAND gate constructed of Metal-Ferroelectric-Semiconductor Field Effect Transistors (MFSFETs) has been investigated. Initially, an inverter circuit was modeled using a n-channel MFSFET with positive polarization for a standard CMOS inverter n-channel transistor and a n-channel MFSFET with negative polarization for the standard CMOS inverter p-channel transistor. The MFSFETs were simulated by using a previously developed MFSFET model which utilized a partitioned ferroelectric layer. Then a 2-input NAND gate was modeled similar to the inverter gate. The data shows that it is feasible to construct a NAND gate with MFSFET transistors.