3D Technology Computer-Aided Design-Based Optimization of Channel Radius Considering Line Edge Roughness on Gate-All-Around Nanowire FET

被引：0

作者：

Son, Dokyun ^{[1
]}

Ko, Kyul ^{[1
]}

Kang, Myounggon ^{[2
]}

Shin, Hyungcheol ^{[1
]}

机构：

[1] Seoul Natl Univ, Dept Elect & Comp Engn, 1 Gwanak Ro, Seoul 151744, South Korea

[2] Korea Natl Univ Transportat, Dept Elect Engn, 2 Daehak Ro, Chungju City 380702, Chungbuk, South Korea

来源：

JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY | 2017年 / 17卷 / 05期

关键词：

Line Edge Roughness (LER); Quantum Effect (QE); Thin Layer Model (TLM);

D O I：

10.1166/jnn.2017.14032

中图分类号：

O6 [化学];

学科分类号：

0703 ;

摘要：

In this work, 3D TCAD-based optimization of channel radius was performed considering line edge roughness (LER) on 5 nm node gate-all-around (GAA) nanowire (NW) FET. As the channel radius is scaled down below 3 nm, we are confronted with seriously reduced driving current due to two major factors where one is small channel carrier density induced by quantum effect (QE) and the other is mobility degradation induced by thickness fluctuation and surface phonon scattering. For the first time, the guideline of channel radius for high performance were studied where the statistical analysis of LER was performed considering QE and thin layer model (TLM) which covers mobility degradation induced by scattering for thin layer.

引用

页码：3060 / 3064

页数：5

共 6 条

[1] Characteristics According to Parameters of Line Edge Roughness in Ultra-Scaled Gate-All-Around Nanowire FET
Son, Dokyun
Ko, Kyul
Woo, Changbeom
Kang, Myounggon
Shin, Hyungcheol
[J]. JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, 2017, 17 (10) : 7179 - 7182
[2] Optimization of 3D Stacked Nanosheets in 5nm Gate-all-around Transistor Technology
Gundu, Anil Kumar
Kursun, Volkan
[J]. 34TH IEEE INTERNATIONAL SYSTEM ON CHIP CONFERENCE (SOCC), 2021, : 25 - 28
[3] Compact modeling of 3D vertical junctionless gate-all-around silicon nanowire transistors towards 3D logic design
Mukherjee, Chhandak
Poittevin, Arnaud
O'Connor, Ian
Larrieu, Guilhem
Maneux, Cristell
[J]. SOLID-STATE ELECTRONICS, 2021, 183
[4] III-V Gate-all-around Nanowire MOSFET Process Technology: From 3D to 4D
Gu, J. J.
Wang, X. W.
Shao, J.
Neal, A. T.
Manfra, M. J.
Gordon, R. G.
Ye, P. D.
[J]. 2012 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2012,
[5] 3D Modeling of Spatio-temporal Heat-transport in III-V Gate-all-around Transistors Allows Accurate Estimation and Optimization of Nanowire Temperature
Wahab, Muhammad Abdul
Shin, SangHoon
Alam, Muhammad Ashraful
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 62 (11) : 3595 - 3604
[6] In vivo MRI-based 3D FSI RV/LV models for human right ventricle and patch design for potential computer-aided surgery optimization
Yang, Chun
Tang, Dalin
Haber, Idith
Geva, Tal
del Nido, Pedro J.
[J]. COMPUTERS & STRUCTURES, 2007, 85 (11-14) : 988 - 997

← 1 →