Modeling a Floating-Gate Memristive Device for Computer Aided Design of Neuromorphic Computing

Memristive technology is still not mature enough for the very large-scale integration necessary to obtain practical value from neuromorphic computing. While nonvolatile floatinggate "synapse transistors" have been implemented in very largescale integrated neuromorphic systems, their large footprint still constrains an upper bound on the overall performance. A two-terminal floating-gate memristive device can combine the technological maturity of the floating-gate transistor and the conceptual novelty of the memristor using a standard CMOS process. In this paper, we present a top-down computer aided design framework of the floating-gate memristive device and show its potential in neuromorphic computing. Our framework includes a Verilog-A model, small-signal schematics, a stochastic model, Monte-Carlo simulations, layout, DRC, LVS, and RC extraction.