A new method for characterization of gate overlap capacitances and effective channel size in MOSFETs

被引：0

作者：

Tomaszewski, Daniel ^{[1
]}

Gluszko, Grzegorz ^{[1
]}

Kucharski, Krzysztof ^{[1
]}

Malesinska, Jolanta ^{[1
]}

机构：

[1] ITE, Div Silicon Microsyst & Nanostruct Technol, Ul Okulickiego 5E, PL-05500 Piaseczno, Poland

来源：

SOLID-STATE ELECTRONICS | 2019年 / 159卷

关键词：

MOSFET; Test structure; Parameter extraction; C-V characteristics; Overlap capacitances; Channel shortening; Channel narrowing; PARASITIC CAPACITANCES; EXTRACTION;

D O I：

10.1016/j.sse.2019.03.058

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Methods for characterization of MOSFET gate overlap capacitances are briefly discussed. Considerations of their shortcomings due to the neglected shortening and/or narrowing of the MOSFET channel in relation to its drawn size have led to development of a new method for a simultaneous extraction of the gate overlap capacitances and of the channel width and length variations. The approach is presented and illustrated using experimental data obtained by C-V measurements of the MOSFETs in a CMOS test structure. The characterization results are compared with the parameters obtained via I-V measurements of the corresponding devices.

引用

页码：184 / 190

页数：7

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