Gate-stack engineered NBTI improvements in high-voltage logic-for-memory high-κ/metal gate devices

被引：0

作者：

O'Sullivan, B. J. ^{[1
]}

Ritzenthaler, R. ^{[1
]}

Rzepa, G. ^{[2
]}

Wu, Z. ^{[1
]}

Litta, E. Dentoni ^{[1
]}

Richard, O. ^{[1
]}

Conard, T. ^{[1
]}

Machkaoutsan, V. ^{[3
]}

Fazan, P. ^{[3
]}

Kim, C. ^{[4
]}

Franco, J. ^{[1
]}

Kaczer, B. ^{[1
]}

Grasser, T. ^{[2
]}

Spessot, A. ^{[1
]}

Linten, D. ^{[1
]}

Horiguchi, N. ^{[1
]}

机构：

[1] IMEC, Leuven, Belgium

[2] TU, Vienna, Austria

[3] Micron, Boise, ID USA

[4] SK Hynix, Ichon, South Korea

来源：

2019 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2019年

关键词：

Logic for memory; NBTI; defect band access; AlOx cap;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Potential solutions for the reliability challenges of high-kappa metal gate (HKMG) integration into DRAM high-voltage peripheral logic devices are reported. A detailed study of Negative Bias Temperature Instability (NBTI)-degradation, supported by physical analysis, assessing the impact of various tuning components within the stack (interface layer, high-kappa fluorination and/or cap, metal gate) is presented. The presence of Nitrogen throughout the HKMG stack can originate either from high-k processing or metal-nitride gate electrode. It is shown that preventing nitrogen diffusion towards the Si/SiO2 interface region, together with AlOx (and F) incorporation at the HKMG interface, can tune device threshold voltage and modulate access to donor trap-defect bands. The result of these effects is a vast improvement in NBTI performance.

引用

页数：8

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