Architectural Power Macromodeling Technique for DSP Architectures

A key challenge in the design of low power digital systems is the fast and accurate estimation of power dissipation. In this paper, we present a look-up-table (LUT) based power macromodeling technique for digital signal processing (DSP) architecture in terms of the statistical knowledge of their primary inputs/ouputs. During the power estimation procedure, the sequence of an input stream is generated by a genetic algorithm (GA) using input metrics. Then, a Monte Carlo zero-delay simulation is performed and a power dissipation macromodel function is built from power dissipation results. From then on, this macromodel function can be used to estimate power dissipation of the system just by using the statistics of the macro-block's primary inputs/outputs. The most important contribution of the method is that it allows fast power estimation of intellectual property (IP) based design by a simple addition of individual power consumptions. This makes the power modelling of SoCs an easy task that permits evaluation of power features at the architectural level. In order to evaluate our model, we have constructed IP-based DSP system using different IP macro-blocks. In experiments with individual IP macro-blocks, the results are effective and highly correlated, with an average error of just 1-3%.