A Modeling Framework for NBTI Degradation Under Dynamic Voltage and Frequency Scaling

被引:47
|
作者
Parihar, Narendra [1 ]
Goel, Nilesh [2 ]
Chaudhary, Ankush [1 ]
Mahapatra, Souvik [1 ]
机构
[1] Indian Inst Technol, Dept Elect Engn, Bombay 400076, Maharashtra, India
[2] Sandisk India, Bengaluru 560103, India
关键词
Dynamic voltage and frequency scaling (DVFS); high-K metal gate (HKMG); negative bias temperature instability (NBTI); reaction-diffusion (RD) model; transient trap occupancy model (TTOM); BIAS TEMPERATURE INSTABILITY; INTERFACE-TRAP GENERATION; AC NBTI; SION; PERSPECTIVE; DEPENDENCE; DC;
D O I
10.1109/TED.2016.2519455
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A modeling framework is proposed to predict the degradation and recovery of threshold voltage shift (Delta V-T) due to negative bias temperature instability. Double interface reaction-diffusion model with transient trap occupancy model is used to predict the generation and recovery of interface traps (Delta V-IT). Empirical stretched exponential equations are used to capture hole trapping and detrapping in preexisting traps (Delta V-HT). The framework consists of uncoupled contributions from Delta V-IT and Delta V-HT and is capable of accurately predicting the ultrafast measured Delta V-T during dc, arbitrary multicycle dc, ac, and mixed-mode dc-ac stress. It can predict pulse duty cycle and frequency dependence of ac degradation and also dynamic voltage and frequency scaling waveforms encountered in actual circuits.
引用
收藏
页码:946 / 953
页数:8
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