Manufacturing cycle time reduction using balance control in the semiconductor fabrication line

被引:23
|
作者
Lee, YH [1 ]
Kim, T [1 ]
机构
[1] Yonsei Univ, Sch Comp & Ind Engn, Seoul 120749, South Korea
关键词
balance; bottleneck scheduling; utilization; cycle time reduction;
D O I
10.1080/0953728021000014954
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
In semiconductor manufacturing, wafer fabrication is the most complicated and important process, and is composed of several hundred process steps and involves several hundred machines. The productivity of the manufacturing process depends mainly on controlling the balance of WIP (work-in-progress) flow to achieve maximum throughput under short manufacturing cycle times. This paper discusses how to determine the proper WIP level for operations, against which balance status can be measured. Balance measurement can be applied in mathematical modelling for bottleneck scheduling and operations management of the fabrication line. Performances are evaluated through computational experiments to show that balance driven management leads to 15-33% more production in 21% shorter manufacturing cycle time than production driven management.
引用
收藏
页码:529 / 540
页数:12
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