Layout based full chip thermal simulations of stacked 3D integrated circuits

被引：0
|
作者：
Raman, A
Turowski, M
Mar, M
机构：
来源：
ELECTRONIC AND PHOTONIC PACKAGING, ELECTRICAL SYSTEMS AND PHOTONIC DESIGN AND NANOTECHNOLOGY - 2003 | 2003年
关键词：
3D IC stack; localized heating; inter-layer dielectric (ILD); thermal vias; simulations;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents full-chip scale detailed thermal simulations of three-dimensional (31)) integrated circuit (IC) stacks. The inter-layer dielectric (ILD) and inter-metal dielectric (IMD) materials inside 3D IC stacks may cause extensive localized heating. The influence of multiple layers of dielectrics on heat trapping inside the 31) stack is analyzed. Different methods to minimize such localized heating are studied. It is shown that the use of thermal vias is very effective in heat dissipation from the hot spots. Comparisons are made between several 3D IC configurations to verify these conclusions.
引用
收藏
页码：159 / 164
页数：6
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