共 50 条
- [1] Layout based 3D thermal simulations of integrated circuits components [J]. COMPUTATIONAL SCIENCE - ICCS 2004, PROCEEDINGS, 2004, 3039 : 1029 - 1036
- [2] Layout based full chip thermal simulations of stacked 3D integrated circuits [J]. ELECTRONIC AND PHOTONIC PACKAGING, ELECTRICAL SYSTEMS AND PHOTONIC DESIGN AND NANOTECHNOLOGY - 2003, 2003, : 159 - 164
- [3] 3D Integrated Circuits Layout Optimization Game [J]. ARTIFICIAL INTELLIGENCE AND SOFT COMPUTING, ICAISC 2017, PT II, 2017, 10246 : 444 - 453
- [4] Fast Thermal Simulations of Vertically Integrated Circuits (3D ICs) Including Thermal Vias [J]. 2012 13TH IEEE INTERSOCIETY CONFERENCE ON THERMAL AND THERMOMECHANICAL PHENOMENA IN ELECTRONIC SYSTEMS (ITHERM), 2012, : 588 - 596
- [5] Thermal modeling and design of 3D integrated circuits [J]. 2008 11TH IEEE INTERSOCIETY CONFERENCE ON THERMAL AND THERMOMECHANICAL PHENOMENA IN ELECTRONIC SYSTEMS, VOLS 1-3, 2008, : 1139 - 1145
- [8] A Comprehensive Platform for Thermal Studies in TSV-based 3D Integrated Circuits [J]. 2014 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2014,
- [10] New Layout Design Methodology for Monolithically Integrated 3D CMOS Logic Circuits Based on Parasitics Engineering [J]. ESSDERC 2015 PROCEEDINGS OF THE 45TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2015, : 258 - 261