Pixel architectures in a HV-CMOS process for the ATLAS inner detector upgrade

被引：6
|
作者：
Degerli, Y. [1 ]
Godiot, S. [2 ]
Guilloux, F. [1 ]
Hemperek, T. [3 ]
Kruger, H. [3 ]
Lachkar, M. [1 ]
Liu, J. [2 ]
Orsini, F. [1 ]
Pangaud, P. [2 ]
Rymaszewski, P. [3 ]
Wang, T. [3 ]
机构：
[1] CEA Saclay, IRFU, F-91191 Gif Sur Yvette, France
[2] Ctr Phys Particules, 163 Ave Luminy, Marseille, France
[3] Univ Bonn, Inst Phys, Nussallee 12, Bonn, Germany
来源：
JOURNAL OF INSTRUMENTATION | 2016年 / 11卷
关键词：
Particle tracking detectors (Solid-state detectors); Pixelated detectors and associated VLSI electronics; Front-end electronics for detector readout;
D O I：
10.1088/1748-0221/11/12/C12064
中图分类号：
TH7 [仪器、仪表];
学科分类号：
0804 ; 080401 ; 081102 ;
摘要：
dIn this paper, design details and simulation results of new pixel architectures designed in LFoundry 150 nm high voltage CMOS process in the framework of the ATLAS high luminosity inner detector upgrade are presented. These pixels can be connected to the FE- I4 readout chip via bump bonding or glue and some of them can also be tested without a readout chip. Negative high voltage is applied to the high resistivity ( > 2 k Omega.cm) substrate in order to deplete the deep n-well charge collection diode, ensuring good charge collection and radiation tolerance. In these pixels, the front- end has been implemented inside the diode using both NMOS and PMOS transistors. The pixel pitch is 50 mu m x 250 mu m for all pixels. These pixels have been implemented in a demonstrator chip called LFCPIX.
引用
收藏
页数：11
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