共 50 条
- [4] A Digital BIST for Phase-Locked Loops [J]. 23RD IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2008, : 134 - 142
- [5] Advanced Digital Phase-Locked Loops [J]. 2013 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2013,
- [6] ON OPTIMUM DIGITAL PHASE-LOCKED LOOPS [J]. IEEE TRANSACTIONS ON COMMUNICATION TECHNOLOGY, 1968, CO16 (02): : 340 - &
- [10] A Novel Calibration Method for Phase-Locked Loops [J]. Analog Integrated Circuits and Signal Processing, 2005, 42 : 77 - 84