Design of Passive UHF RFID Tag in 130nm CMOS Technology

This paper presents a low-power, passive, UHF RFID tag design compatible with EPC (TM) C1G2 protocol. In order to reduce its cost, diode-connected NMOS in a standard CMOS technology is used instead of Schottky diodes. With the help of low-threshold-voltage, triple-well NMOS, a minimum input power of -7.6dBm is achieved. A sub-1V, low temperature-coefficient voltage reference using self-biased mutual compensation is proposed without large resistors to save the chip area. In addition, an energy-aware irregular clock structure, together with clock gating, achieves low power consumption in the baseband processor. The whole tag is implemented in a 130nm CMOS technology and the total chip area is 1200umx1220um.