Fabrication of Strained Ge on Insulator via Room Temperature Wafer Bonding

被引:0
|
作者
Asadollahi, A. [1 ]
Radamson, H. [1 ]
Zabel, T. [1 ]
Hellstrom, P. -E [1 ]
Ostling, M. [1 ]
机构
[1] KTH Royal Inst Technol, Sch ICT, S-16440 Kista, Sweden
关键词
ON-INSULATOR; SIGE; GERMANIUM; SUBSTRATE;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This work describes a strained germanium on insulator (GeOI) fabrication process using wafer bonding and etch-back techniques. The strained Ge layer is fabricated epitaxially using reduced pressure chemical vapor deposition (RPCVD). The strained Ge is grown pseudomorphic on top of a partially relaxed Si0.66Ge0.34 layer. Wafer bonding is performed at room temperature without post-anneal processes and the etch-back steps are performed without mechanical grinding and chemical mechanical polishing (CMP).
引用
收藏
页码:81 / 84
页数:4
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