Impact of device scaling on the 1/f noise performance of deep submicrometer thin gate oxide CMOS devices

This paper presents the effects of technology and geometry scaling on the 1/f noise performance of deep submicrometer transistors taken from four advanced CMOS technologies, namely the 0.13 mu m, 0.18 mu m, 0.25 mu m and 0.35 mu m nodes. For the 0.13 mu m technology node, three different process flavours consisting of the generic (G) process flow, the low voltage/high performance (LV/HP) process flow and the low standby power (LSP) process flow have been investigated. The higher degree of gate dielectric nitridation with technology downscaling from 0.35 mu m node to 0.13 mu m G node has resulted in a severe degradation of the 1/f noise performance of the transistors by approximately three orders of magnitude. On the contrary, the employment of 0.13 mu m LSP transistors have been demonstrated to lower the 1/f noise spectra by approximately two orders of magnitude as compared to the 0.13 mu m LV/HP transistors, which gives the worst 1/f noise performance among the three different process flavours in the 0.13 mu m node. The study of device geometry scaling on 0.13 mu m LSP transistors shows that in general the scaling trend follows the S-Id proportional to W/L-3 rule, where S-Id, W and L represent the current noise spectral density, the active gate width and length of the transistor, respectively. For devices with gate area < 1 mu m(2), a large dispersion in the 1/f noise level can be seen. This phenomenon has been correlated to the existence of Lorentzian-like spectra for small area transistors. The investigation of the effect of scaling the transistor's aspect ratio (W/L) reveals a (S-Id x WL) proportional to (W/L)(2) dependence. (c) 2006 Elsevier Ltd. All rights reserved.