A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth

被引：19
|
作者：
Renukaswamy, Pratap Tumkur [1 ,2 ]
Markulic, Nereo [1 ]
Wambacq, Piet [1 ,2 ]
Craninckx, Jan [1 ]
机构：
[1] IMEC, B-3001 Leuven, Belgium
[2] Vrije Univ Brussel, Dept ETRO, B-1050 Brussels, Belgium
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2020年 / 55卷 / 12期
关键词：
Background calibration; CMOS; digital calibration; FMCW radar; fractional-N SSPLL; frequency-modulated continuous-wave (FMCW); integrating digital-to-analog converter (QDAC); phase-locked loop (PLL); pre-distortion; sawtooth chirp; sub-sampling PLL (SSPLL); two-point modulation (TPM); PHASE-LOCKED-LOOP; FRACTIONAL-N PLL; SUBSAMPLING-PLL; CMOS; MODULATOR; NOISE; NONLINEARITY; TRANSCEIVER; VCO;
D O I：
10.1109/JSSC.2020.3021311
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 10-GHz sub-sampling phase-locked loop (PLL) (SSPLL) with wideband low-noise frequency modulation for frequency-modulated continuous-wave (FMCW) radar applications is presented. It uses a low-power charge-integrating digital-to-analog converter ( QDAC) to tune the voltage-controlled oscillator (VCO) in a two-point modulation architecture. A full background calibration engine corrects for the nonlinearities in the QDAC modulation path. Implemented in a 28-nm CMOS process, the SSPLL consumes 11.7 mW (of which less-than 0.5 mW from the QDAC) to generate a 23.6-MHz/mu s sawtooth chirp-slope with 28-kHz rms-frequency-error for 1.21-GHz chirp-bandwidth.
引用
收藏
页码：3294 / 3307
页数：14
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