High Throughput Architecture for Low Density Parity Check (LDPC) Encoder

被引：0
|
作者：
Anggraeni, Silvia [1 ]
Hussin, Fawnizu Azmadi [1 ]
Jeoti, Varun [1 ]
机构：
[1] Univ Teknol PETRONAS, Dept Elect Engn & Elect, Tronoh 31750, Perak, Malaysia
来源：
2013 IEEE 56TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) | 2013年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper proposes a bit-wise matrix-vector multiplication in the optimization of a proposed low density parity check (LDPC) encoder. Investigation of this proposed architecture is done by implementing five code lengths using one IEEE 802.16e standard code rate. It is shown that the proposed architecture outperforms other works in terms of information throughput ranging from 0.235 to 8.83 times higher. In term of ratio of throughput per area, the proposed method exceeds other works in the range of 1.19 to 6.54 times higher.
引用
收藏
页码：948 / 951
页数：4
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