Low-voltage low-power adaptive biased high-efficiency integrated amplifiers

The principle and application of a novel adaptive biasing topology which reduce the stand-by power dissipation without affecting the transient performance of low-power amplifiers and buffers is presented. The basic adaptive circuit gives a current dependent on the applied input differential voltage. The differential sensitivity can be improved by introducing a very small biasing current, to compensate transistor threshold voltage, whose value can be set according to the transient performance constraints. The proposed topology, in both bipolar and CMOS technologies, can be utilized in the design of high-efficient low-voltage low-power operational amplifiers, for the biasing of both the input stage (to increase dynamically the input source current) and the output stage (to control and limit the output current). The designed amplifiers show a very good behaviour, in terms of efficiency factor, when compared with other adaptive circuits in literature. Simulation results and measurements on a chip prototype are finally presented.