Dynamic voltage scaling aware delay fault testing

被引:0
|
作者
Ali, Noohul Basheer Zain [1 ]
Zwolinski, Mark [1 ]
Al-Hashimi, Bashir M. [1 ]
Harrod, Peter [2 ]
机构
[1] Univ Southampton, Sch Elect & Comp Sci, Elect Syst Design Grp, Southampton SO9 5NH, Hants, England
[2] ARM Ltd, Cambridge CBI 9JN, England
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中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The application of Dynamic Voltage Scaling (D VS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faults. This paper analyses the influence of different vollage/frequency settings on fault detection within a D VS application. In particular, the effect of supply voltage on different types of delay faults is considered This paper presents a study of these problems with simulation results. We have demonstrated that the test application time increases as we reduce the test voltage. We have also shown that for newer technologies we do not have to go to very low voltage levels for delay fault testing. We conclude that it is necessary to test at more than one operating voltage and that the lowest operating voltage does not necessarily give the best fault cover.
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页码:15 / +
页数:2
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