A 15-Gb/s 2:1 multiplexer in 0.18-μm CMOS

被引：15
|
作者：
Chien, Jun-Chau [1 ]
Lu, Liang-Hung
机构：
[1] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan
[2] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan
来源：
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS | 2006年 / 16卷 / 10期
关键词：
high-speed latches; inductive peaking; multiplexer (MUX); optical-fiber communications; selectors; super-dynamic flip-flops;
D O I：
10.1109/LMWC.2006.882384
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
By employing the inductive peaking technique and the super-dynamic flip-flops, a 2:1 multiplexer (MUX) is presented for high-speed operations. The proposed circuit is realized in a 0.18-mu m CMOS process. With a power consumption of 110 mW from a 2-V supply voltage, the fully integrated MUX can operate at an output rate up to 15 Gb/s. From the measured eye-diagrams, the 15-Gb/s half-rate MUX exhibits an output voltage swing of 225 mV and a root-mean-square jitter of 2.7 ps.
引用
收藏
页码：558 / 560
页数：3
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