Design of high-speed low-power parallel-prefix VLSI adders

Parallel-prefix adders offer a highly-efficient solution to the binary addition problem. Several parallel-prefix adder topologies have been presented that exhibit various area and delay characteristics. However, no methodology has been reported so far that directly aims to the reduction of switching activity of the carry-computation unit. In this paper by reformulating the carry equations, we introduce a novel bit-level algorithm that allows the design of power-efficient parallel-prefix adders. Experimental results, based on static-CMOS implementations, reveal that the proposed adders achieve significant power reductions when compared to traditional parallel-prefix adders, while maintaining equal operation speed.